Originally published February 21 2006
Intel debuts new memory chips
by Mike Adams, the Health Ranger, NaturalNews Editor
Intel and most other major other chipmakers decrease the size of the transistors in their chips every two years in accordance with Moore's Law. Intel uses lithography techniques to draw circuit patterns on chips through optical and chemical processes.
The Santa Clara, Calif.-based chip giant has created test chips made on the 45-nanometer process and will likely begin shipping processors, flash, and other chips based on that process in the second half of 2007, according to Mark Bohr, director of process architecture and integration at Intel.
The test chips, produced this month, are static SRAM memory chips containing 153 megabits of memory.
The chips contain over a billion transistors and are nearly the same size as test SRAM chips produced by Intel in 2000 on the then-new 130-nanometer process that contained 18 megabits of memory.
The memory cells on the 45-nanometer test chips take up 0.346 square microns, compared to 2.45 square microns.
A nanometer is a billionth of a meter while a micron is a millionth; a human hair is about 60 to 90 microns in diameter.
Every two years, Intel and most other major other chipmakers shrink the size of the transistors embedded in their chips in accordance with Moore's Law.
Shrinking the transistors in this manner increases overall chip performance, reduces energy consumption and cuts the manufacturing cost per chip.
Right now, Intel is producing chips on the 65-nanometer process, while AMD won't come out with these chips until the second half.
"It does get a little more challenging every time, but we come up with new technology and tricks to keep things going," said Bohr.
One clear part of the process, however, is that Intel will use "dry," or standard, lithography techniques for 45-nanometer chips.
According to Intel, Extreme Ultraviolet lithography (EUV) is "more likely for 22-nanometer" manufacturing, which starts in 2011.
EUV lithography, which has a light source derived from laser beams developed for the Cold War-era Star Wars program, was slated to go into production on the 65-nanometer process, but it has been delayed several times.
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